Loop decoder for josephson memory arrays

Details Loop decoder for josephson memory arrays Loop decoder for josephson memory arrays

H - Electricity

03

K

354/237

H03K 19/195 (2006.01) G11C 11/44 (2006.01) H03K 3/38 (2006.01) H03M 7/00 (2006.01)

Patent

CA 1098216

LOOP DECODER FOR JOSEPHSON MEMORY ARRAYS Abstract of the Disclosure Decoder circuit arrangements for use with Josephson memory device arrays are disclosed. In one circuit of N stages, an input circuit consists of a Josephson junction and a shunting impedance connected across the junction by means of a matched transmission line. The transmission line has two output portions each of which controls the actuation or nonactuation of a pair of devices of circuits similar to the above-described circuit which are disposed in series in a pair of branches of a serially disposed superconducting loop of a first stage. Each branch has a serially disposed address gate to which true and complement address signals are applied. Each succeeding stage is similar to the first stage except that each branch of each succeeding stage contains twice as many circuits similar to the above-mentioned first stage circuit. Each stage provides a pair of output portions from each circuit in each branch and these outputs are connected so that the outputs of one circuit are connected to an actuable device in each branch of a succeeding stage. YO9-76-067 -1-

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