Loop status verification system

Details Loop status verification system Loop status verification system

H - Electricity

04

B

379/2

H04B 3/46 (2006.01) H04M 3/30 (2006.01) H04M 11/04 (2006.01) H04Q 3/60 (2006.01) H04Q 1/44 (2006.01)

Patent

CA 1316277

Abstract of the Disclosure A system is disclosed for verifying the integrity of each one of a number of communication paths, illustratively telephone subscriber loops, that runs between a near end location, illustratively a telephone company central office, and corresponding remote ("far end") location(s). This system utilizes circuitry, such as a line verification module, that is located at the far end of each such path to impart a selected test signal thereto. In one embodiment, the circuitry detects one or more conditions thereat (e.g. loop current and loop voltage) that are indicative of normal operation of the path, e.g. proper on-hook and off-hook conditions. As long as the path is normally operating at the far end, this circuitry transmits a test signal, e.g. a selected one of a number of sub-audible frequencies, over the path to the near end. This test signal is chosen to be substantially transparent to normal communication (e.g. local telephone company signalling and transmission frequencies) occurring over that path. In a second embodiment, the circuitry continuously transmits the test signal over the path. With either embodiment, the circuitry automatically adjusts that level of the test signal such that this signal, as it appears on the path, remains at an approximately constant amplitude regardless of whether that path is in an on-hook or off-hook condition. Central office monitoring circuitry, illustratively containing a line test unit and a controller, is connected to this as well as every other path being verified at the near ends thereof. For each path being verified, this monitoring circuitry first "learns" the frequency associated with the test signal appearing over that path, and thereafter detects any cessation or unexpected change in the test signal (i.e. a mismatch against a prescribed test signal that is expected to appear over that path) occurring at the near end thereof that is indicative of a possible loss of path (e.g. loop) integrity and, in turn, provides an appropriate notification specifying that loss.

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