Low capacitance self-aligned semiconductor electrode...

Details Low capacitance self-aligned semiconductor electrode... Low capacitance self-aligned semiconductor electrode...

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H01L 29/40 (2006.01) H01L 21/28 (2006.01) H01L 21/3213 (2006.01) H01L 21/335 (2006.01) H01L 29/10 (2006.01) H01L 29/45 (2006.01) H01L 29/772 (2006.01)

Patent

CA 1167981

?2,551 ABSTRACT OF THE DISCLOSURE Semiconductor electrode structure with low parasitic capacitance and method for forming low capacitance first and second electrodes in a semiconductor device, such as a static induction transistor, while avoiding the requirement for precision mask alignment and mask to mask registration. During formation of electrode con- tacts, the first electrodes are protected by silicon nitride and a low resistivity silicon layer is grown over the semiconductor wafer, forming epitaxial regions over the second electrodes and a polycrystalline region over protected portions of the wafer. The silicon layer is selectively etched by a mixture which removes the polycrystalline region but does not appreciably affect the epitaxial regions. Second electrode metallic con- tacts are made in enlarged regions of the second elec- trodes where mask alignment is not critical. The reduction in contact window overlap by metallic contacts reduces parasitic capacitance.

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