Low current cmos translator circuit

Details Low current cmos translator circuit Low current cmos translator circuit

H - Electricity

03

K

328/106

H03K 19/018 (2006.01) H03K 12/00 (2006.01) H03K 19/0185 (2006.01)

Patent

CA 1304138

ABSTRACT OF THE DISCLOSURE A low current CMOS translator arrangement is disclosed that utilizes a low current inverting stage, having a peak current requirement, fed by a constant current source at a supply node that also has a capacitor coupled to it. This low current inverter is useful for a number of applications, including generating a sinusoidal signal when it is coupled to a crystal. When one or more are cascaded and coupled to a square wave input signal, the arrangement becomes a low current translator that level-shifts, or translates, the input signal having a first voltage range to a translated square wave output signal having a second voltage range. In another embodiment called a low current squaring translator, a squaring stage is coupled between the low current inverter and a low current translator that includes one or more inverting stage.s This arrangement is able to achieve an output signal that maintains a precise duty cycle with low noise at a very low current.

601700

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