Low jitter digital delay generator

Details Low jitter digital delay generator Low jitter digital delay generator

H - Electricity

03

K

328/92

H03K 5/135 (2006.01) G01R 13/34 (2006.01) H03K 23/66 (2006.01)

Patent

CA 1275309

Abstract of the Disclosure A programmable delay generator is based upon an asynchronous or ripple counter the stages of which change state at definably different times. A full terminal count is decoded stage which changes state at a unique time which is different from the time at which any other stage changes, for thereby defining an unambiguous delay period. A partial terminal count programmably determines the length of circuit output and the reloading of the ripple counter with a programmable, time delay determining, initial value.

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