Low-latency viterbi survivor memory architecture and method...

Details Low-latency viterbi survivor memory architecture and method... Low-latency viterbi survivor memory architecture and method...

H - Electricity

03

M

H03M 13/23 (2006.01) H04L 1/00 (2006.01)

Patent

CA 2730860

In various aspects, the disclosure describes systems and methods for decoding of convolutionally encoded signals representing, for example, telecommunications signals such as command or content signals used in digital telecommunications. In various embodiments such aspects of the disclosure provide systems and methods for improving the efficiency, speed, and power consumption of such processes by providing architectures and methods for processing various parts of the encoded data records in parallel, using multiple and optionally specially-designed, dedicated memory registers and multiplexers.

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