Low power antifuse sensing scheme with improved reliability

Details Low power antifuse sensing scheme with improved reliability Low power antifuse sensing scheme with improved reliability

G - Physics

11

C

G11C 17/18 (2006.01) G11C 7/12 (2006.01)

Patent

CA 2692887

Generally, a method and circuit for improving the retention and reliability of unprogrammed anti-fuse memory cells. This is achieved by minimizing the tunneling current through the unprogrammed anti-fuse memory cells which can cause eventual gate oxide breakdown. The amount of time a read voltage is applied to the anti-fuse memory cells is reduced by pulsing a read voltage applied to a wordline connected to the unprogrammed anti-fuse memory cells, thereby reducing the tunneling current. Further tunneling current can be reduced by decoupling the unprogrammed anti-fuse memory cells from a sense amplifier that can drive the corresponding bitline to VSS.

En général, méthode et circuit visant à améliorer la retenue et la fiabilité des cellules de mémoire antifusibles non programmées. Ce but est atteint en minimisant le courant tunnel traversant ces cellules de mémoire, ce qui peut provoquer la détérioration de l'oxyde de grille de ces cellules. La durée d'application d'une tension relevée sur les cellules de mémoire antifusibles est réduite par la pulsation de ladite tension relevée appliquée au canal mot branché aux cellules, ce qui réduit le courant tunnel. Il est possible de réduire encore davantage ce courant tunnel et désaccouplant les cellules mémoires antifusibles non programmées d'un amplificateur de détection qui peut activer le canal bit correspondant vers un simulateur VSS.

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