Low-power battery backup circuit for semiconductor memory

Details Low-power battery backup circuit for semiconductor memory Low-power battery backup circuit for semiconductor memory

G - Physics

11

C

352/82

G11C 11/34 (2006.01) G11C 5/14 (2006.01)

Patent

CA 1162648

- 1 - ABSTRACT: A battery backup circuit for an MOS memory which has a multiplexed pin (WE) that functions to provide backup power to a memory cell array (50) upon loss of primary power Vcc. A voltage comparator (10) detects when the primary power Vcc becomes less than the backup voltage on the WE terminal. Upon detection of loss of primary power the memory cell array (50) is powered by a connection to the WE terminal. A primary power status signal (POK) indicates the status of the primary power and is driven to a state indicating insufficient circuit voltage for normal operation when Vcc drops below an acceptable limit or when there is inadequate substrate bias. The circuit of the present invention further generates an inhibit signal to prevent the operation of peripheral circuits (70) to write data into the memory cell array (50) upon detection of a failure of primary power. The inhibit signal is generated when primary power is lost or when the substrate bias is inadequate. A low-power auxiliary pump generator (92) provides a sufficient substrate bias to maintain the data pattern in the memory cell array (50) during the backup mode.

370211

Affiliated with

Also associated with

Rating

Low-power battery backup circuit for semiconductor memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low-power battery backup circuit for semiconductor memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low-power battery backup circuit for semiconductor memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1052500