Low-power bicmos/ecl sram

Details Low-power bicmos/ecl sram Low-power bicmos/ecl sram

G - Physics

11

C

G11C 11/417 (2006.01)

Patent

CA 2163147

A SRAM includes an ECL input buffer connected between an address bus and a W-OR predecoder array. The logic output of the W-OR predecoder array is applied to a level translator array and level shifted. The level shifted output of the level translator array is supplied to a plurality of self-resetting word-line decoder and driver (WLDD) circuits. The WLDD circuits supply activation pulses to selected blocks of memory in a memory cell array. Sense amplifiers sense and latch-in the data stored in the activated selected blocks of memory. The design of the W-OR predecoder array, level translator array, WLDD circuits and sense amplifiers is such to reduce the overall power consumption of the SRAM.

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