Low-power clocking circuit

Details Low-power clocking circuit Low-power clocking circuit

H - Electricity

03

K

328/193

H03K 17/00 (2006.01) H03K 19/00 (2006.01)

Patent

CA 1327063

ABSTRACT OF THE DISCLOSURE According to the present invention, the current drawn by a switchable electronic circuit is reduced or minimized. The method and apparatus are appropriate for CMOS circuitry. A circuit having a plurality of non or minimal power consumption logic elements and at least first and second switchable logic elements may be controlled by the following method. The method comprises the steps of enabling the first logic element to determine itself, enabling the second logic element to determine itself, and wherein the step of enabling the second logic element is not commenced until the first logic element is substantially determined. With such a method and apparatus, the current drawn by the circuit is effectively distributed over a period of time.

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