Low-power high-performance memory cell and related methods

Details Low-power high-performance memory cell and related methods Low-power high-performance memory cell and related methods

G - Physics

11

C

G11C 11/40 (2006.01) G11C 11/407 (2006.01) H01L 27/105 (2006.01) H03K 3/012 (2006.01) H03K 19/00 (2006.01)

Patent

CA 2479682

An integrated circuit comprising a first NMOS transistor; a first PMOS transistor; a second NMOS transistor; a second PMOS transistor; a first bias voltage node coupled to a first source/drain of the second PMOS; a third bias voltage node coupled to a gate of the first PMOS transistor; a fourth bias voltage node coupled to a gate of the first PMOS transistor; a pull-up node coupling a second source/drain of the firs NMOS transistor to a first source/drain of the first PMOS transistor; a pull-down node coupling a second source/drain of the second PMOS transistor to a first source/drain of the second NMOS transistor; an input node; a storage node coupling a second source/drain of the first PMOS transistor to a second source/drain of the second NMOS transistor; an output node; and input switch coupled to controllably communicate an input data value from the input node to a gate to a gate of the first NMOS transistor and to a gate of the second PMOS transistor; and an output switch coupled to controllably communicate a stored data value from the storage node to the output node.

L'invention concerne un circuit intégré comprenant les éléments suivants: premier transistor NMOS; premier transistor PMOS; second transistor NMOS; second transistor PMOS; premier noeud de tension de polarisation couplé à un premier ensemble source/drain du premier transistor NMOS; second noeud de tension de polarisation couplé à un premier ensemble source/drain du second transistor PMOS; troisième noeud de tension de polarisation couplé à une grille du premier transistor PMOS; quatrième noeud de tension de polarisation couplé à une grille du second transistor NMOS; noeud d'excursion haute pour le couplage entre un second ensemble source/drain du premier transistor NMOS et un premier ensemble source/drain du premier transistor PMOS; noeud d'excursion basse pour le couplage entre un second ensemble source/drain du second transistor PMOS et un premier ensemble source/drain du second transistor NMOS; noeud d'entrée; noeud de stockage pour le couplage entre un second ensemble source/drain du premier transistor PMOS et un second ensemble source/drain du second transistor NMOS; noeud de sortie; et commutateur d'entrée couplé pour la transmission contrôlable d'une valeur de données d'entrée depuis le noeud d'entrée vers une grille du premier transistor NMOS et une grille du second transistor PMOS; et commutateur de sortie couplé pour la transmission contrôlable d'une valeur de données stockée depuis le noeud de stockage vers le noeud de sortie.

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