Low power oscillator and power down method

H - Electricity – 02 – J

Patent

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Details

H02J 9/00 (2006.01) G06F 1/14 (2006.01) G06F 1/32 (2006.01) H01L 23/50 (2006.01) H04B 1/16 (2006.01)

Patent

CA 2393651

A low power Oscillator Circuit and a method for using this oscillator in a power down mode is taught herein. The power down method (Figure 1) is accomplished by turning off a crystal oscillator (1) and standard circuitry (2) and using only the low power relaxation oscillator (3) and realtime counters that are part of the oscillator control circuit (4). To provide precision timing while in power down mode, the oscillator frequency of the low power relaxation oscillator (3) is measured in standard operating mode by the oscillator control circuit (4) using the precision crystal oscillator (1) as a reference frequency. By accurately measuring the low power relaxation oscillator (3) frequency, the length of the power down time can be programmed using a real time counter in the oscillator control circuit (4). Furthermore, when exiting from power down mode, the oscillator control circuit can use a second real time counter to first turn on the crystal oscillator (1) and let it stabilize before turning on the standard circuitry (2). Furthermore, after precisely measuring the low power relaxation oscillator (3) frequency, the low power relaxation oscillator (3) and oscillator control circuit (4) is used to precisely measure the crystal oscillator (1) power up time and adjust crystal oscillator (1) bias currents to optimize power consumption versus crystal oscillator (1) power-up time.

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