Low-voltage cmos output buffer

Details Low-voltage cmos output buffer Low-voltage cmos output buffer

H - Electricity

03

K

328/127

H03K 19/094 (2006.01) G06F 13/40 (2006.01) G11C 7/10 (2006.01) H03K 19/003 (2006.01) H03K 19/0185 (2006.01)

Patent

CA 2019984

LOW-VOLTAGE CMOS OUTPUT BUFFER ***** ABSTRACT OF THE DISCLOSURE A CMOS push-pull output buffer is powered by a low-voltage (e.g., +3.3 V) supply, but is able to withstand elevation of its output node to higher voltage without sinking large currents into the low-voltage supply. Thus, this buffer is able tooperate tied to a bus that has various higher-voltage sources also operating on the bus. The P-channel pull-up transistor of this buffer has another P-channel transistor connecting its gate to the output node so that this gate will follow the voltage of the output node and thus keep the pull-up transistor from conducting from the outputnode to the power supply. The inverter which drives this gate of the P-channel pull- up transistor is also protected from reverse current into its low-voltage power supply by a series N-channel transistor which will exhibit body effect and is sized to present a significant resistance. *****

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