Low voltage one transistor flash eeprom cell using...

Details Low voltage one transistor flash eeprom cell using... Low voltage one transistor flash eeprom cell using...

H - Electricity

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H01L 29/788 (2006.01) G11C 16/04 (2006.01) G11C 16/10 (2006.01) G11C 16/14 (2006.01) G11C 16/16 (2006.01) G11C 16/34 (2006.01) H01L 27/115 (2006.01)

Patent

CA 2184724

A single transistor electrically erasable programmable memory device capable of being programmed and erased using Fowler-Nordheim tunneling and capable of being operated using low voltages. Portions of each of the source and drain regions overlap with the first gate dielectric layer, and the interpoly dielectric layer is chosen to have a high dielectric constant so as to maximize the capacitive coupling ratio between floating gate, control gate, source, and drain. The logical condition of cells in the array is set by first elevating a block of cells to a high voltage threshold and by individually lowering the voltage threshold of selected cells.

Un dispositif mémoire mono-transistor effaçable et programmable électriquement par effet tunnel de Fowler-Nordheim peut être mis en oeuvre à basses tensions. Des parties de chacune des zones source et de chaque zone drain sont en chevauchement avec la couche diélectrique de la première grille de commande, et la couche diélectrique du dispositif d'interpolation est choisie pour sa constante diélectrique élevée de façon à obtenir un taux de couplage capacitif aussi élevé que possible entre grille flottante, grille de commande, source et drain. L'initialisation de l'état logique des cellules s'obtient en élevant d'abord un bloc de cellules à un seuil de tension élevé, puis en abaissant individuellement le seuil de tension des cellules sélectionnées.

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