Lssd-testable d-type edge-trigger-operable latch with...

Details Lssd-testable d-type edge-trigger-operable latch with... Lssd-testable d-type edge-trigger-operable latch with...

H - Electricity

03

K

328/132

H03K 3/037 (2006.01) G01R 31/28 (2006.01) G01R 31/3185 (2006.01) G06F 11/26 (2006.01)

Patent

CA 1213005

ABSTRACT OF THE DISCLOSURE A LSSD testable latch circuit apparatus is disclosed which has systems operational and LSSD testing operational modes. The apparatus is arranged with first and second groups of flip-flops, each group having three flip-flops. Control means allows for selective operation of the first group of flop-flops as a D-type edge triggered latch during the systems operational mode and of the first and and second groups as a three-stage shift register during the LSSD testing operational mode. The control means also allows the D-type edge-triggered latch to have override asynchronously set and/or reset control.

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