Management of erased blocks in flash memories

Details Management of erased blocks in flash memories Management of erased blocks in flash memories

G - Physics

06

F

G06F 12/02 (2006.01)

Patent

CA 2536992

The invention relates to a method for managing the erasure process in a memory system comprising individually erasable memory blocks (SB) that can be addressed with the aid of real memory block addresses (SBA). Said memory blocks are sub-divided into a plurality of writable sectors and can be addressed by means of an address conversion that uses an allocator table (ZT) to convert logical block addresses (LBA) into one of the respective memory block addresses (SBA). According to the invention, the allocator table (ZT) is sub-divided into at least one useful data area (NB) and a buffer block area (BB). The invention is characterised in that a first identifier erased (ER), indicating the physical erasure status and a second identifier content erased (CER), indicating the logical erasure status, is set for each memory block (SB) in the allocator table (ZT).

L'invention concerne un procédé de gestion de l'effacement dans un système à mémoire comprenant des blocs mémoire (SB) effaçables individuellement, adressables au moyen d'adresses de blocs mémoire réelles (SBA), lesdits blocs mémoire étant subdivisés en une pluralité de secteurs inscriptibles et étant adressables au moyen d'une conversion d'adresse utilisant une table d'affectation (ZT) pour convertir des adresses de blocs logiques (LBA) en l'une des adresses de blocs mémoire réelles respectives (SBA). La table d'affectation (ZT) est subdivisée en au moins une zone de données utiles (NB) et une zone à bloc tampon (BB). L'invention est caractérisée en ce qu'à chaque bloc mémoire (SB) dans la table d'affectation (ZT) sont associés un premier identificateur <= effacé >= (ER) indiquant l'état d'effacement physique, et un second identificateur <= contenu effacé >= (CER) indiquant l'état d'effacement logique.

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