Management system for the memory of processor or microprocessor

G - Physics – 06 – F

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354/222

G06F 9/06 (2006.01) G06F 12/00 (2006.01)

Patent

CA 1205918

ABSTRACT OF THE DISCLOSURE System for the management of the physical memory of a processor, incorporating a table of segment descriptive registers connected to the processor and the means transforming a virtual address supplied by the processor into a physical address an order to permit the performance of a task, on the basis of real pages and segments contained in a physical memory, said virtual address containing at least one virtual page number, the binary value of a checking index of the first descriptive register of a physical segment in the memory corresponding to a task to be performed, and the offset value of the start of the physical segment, with respect to the start of the corresponding real page, wherein it also comprises a base register which is loaded, for each virtual address, by the base address of the descriptive register corresponding to the task to be performed, said base address being supplied by the processor, the descriptive register table having inputs connected to the outputs of a logic adder, which receives. on the one hand the binary value of the base address of the first descriptive register, and on the other hand the binary value of the index corresponding to this register, the outputs of the adder checking one of the inputs of the descriptive register table, wherein one of the descriptive registers of the table contains control bits received by the processor and which make it possible for the latter to check whether, for the segment to which the processor must have access, said processor must operate in the local or overall mode, whether it must process an input - output operation, or an access to the memory. B 7323 C/DC

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