Managing high speed slow access channel to slow speed cyclic...

Details Managing high speed slow access channel to slow speed cyclic... Managing high speed slow access channel to slow speed cyclic...

G - Physics

06

F

G06F 13/14 (2006.01) G06F 12/08 (2006.01)

Patent

CA 2046709

A cached DASD controller is illustrated which is attached to a high speed serial channel, such as an optical fiber channel. The data rate of the serial channel is much greater than the data rate of a DASD connected to the controller. The serial channel has a relatively long propagation time such that synchronous operations between the host processor 10 and the DASD cannot be efficiently performed. Operation of a data transfer, whether read or write between the host processor 10 and the DASD is monitored. Whenever a copy of the track contents and in cache and the DASD reaches either an index mark with or a break point from a roll mode operation or certain write operations occur resulting in predetermined data being stored in cache, then a GOCACHE flag is set in a control portion of the controller. The device operations are then momentarily idled while cache to host processor operations are enabled.

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