Mask surrogate semiconductor process

Details Mask surrogate semiconductor process Mask surrogate semiconductor process

H - Electricity

01

L

356/149

H01L 21/24 (2006.01) H01L 21/033 (2006.01) H01L 21/225 (2006.01) H01L 21/266 (2006.01) H01L 21/336 (2006.01)

Patent

CA 1277437

Abstract of the Disclosure A mask-defect-immune process for making semiconductor devices. The process features the creation of one or more surrogate masks in semiconductor wafer material per se, thus to eliminate the requirement that plural masks be used, and that plural mask alignments be performed. In all ways of practicing the invention, one surrogate mask in created in a dopant-opaque region.

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