Massively reduced instruction set processor

Details Massively reduced instruction set processor Massively reduced instruction set processor

G - Physics

06

F

G06F 17/00 (2006.01) G06F 7/38 (2006.01) G06F 15/00 (2006.01) H04L 12/56 (2006.01) H04L 29/06 (2006.01)

Patent

CA 2443347

This invention is directed to a method and apparatus for providing low, predictable latencies in processing IP packets. The apparatus provides a specialized microprocessor or hardwired circuitry to process IP packets for video communications and control of the video source without an operating system. The method relates to operation of a microprocessor which is suitably arranged to carry out the steps of the method. The method includes details of operation of the specialized microprocessor.

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