Master image chip organization technique or method

Details Master image chip organization technique or method Master image chip organization technique or method

H - Electricity

05

K

356/122, 356/8

H05K 1/16 (2006.01) H01L 23/528 (2006.01) H01L 27/118 (2006.01) H05K 3/10 (2006.01)

Patent

CA 1133146

MASTER IMAGE CHIP ORGANIZATION TECHNIQUE OR METHOD ABSTRACT Semiconductor chips are optimally structured to facilitate the maximum number of devices and circuits, and to facili- tate fabrication of a wide variety of large scale integrated part numbers. Essentially, none of the semiconductor sur- face is dedicated for signal and power wiring channels. A master image wiring structure is provided which resides over the semiconductor surface and beneath a power surface. This master image wiring structure makes it possible to person- alize the power and signal wiring for a multiple power surface structure. The combined master image structure provides a means for optimally allocating semiconductor area for devices, functional units (micro and macro) and signal and power wiring to facilitate improved density and perfor- mance. FI9-78-014

337643

Affiliated with

Also associated with

Rating

Master image chip organization technique or method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Master image chip organization technique or method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Master image chip organization technique or method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-815408