Master/slave clock system

Details Master/slave clock system Master/slave clock system

G - Physics

04

C

58/7

G04C 13/00 (2006.01) G04G 7/00 (2006.01)

Patent

CA 1211944

Abstract A master/slave clock system including a slave clock configured for inexpensive and relible control from the master. Each slave clock has an unregulated d-c supply adapted to be supplied with a-c power from the master clock. Threshold switching means in each slave clock is coupled across the d-c supply to sense an abnormally low d-c voltage level intentionally created by lowering the a-c supply level from the master. The threshold switching means switches the clock from the normal operating mode to the set mode where time is incremented at a predetermined rate for a duration controlled by the master clock in order to controllably set all slave clocks in the system to the correct time of day. The system conveniently allows all slaves to be reset to the same time when time is reset at the master, provides for automatic recovery after power failures, and provides a convenient means for automatically resynchronizing all slave clocks twice a day.

453045

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