Means and method for disabling access to a memory

Details Means and method for disabling access to a memory Means and method for disabling access to a memory

G - Physics

11

C

340/70, 352/82

G11C 29/00 (2006.01) G06K 19/073 (2006.01) G07F 7/10 (2006.01) G09C 5/00 (2006.01) G11C 8/20 (2006.01) H01L 23/52 (2006.01)

Patent

CA 1182219

MEANS AND METHOD FOR DISABLING ACCESS TO A MEMORY Abstract An integrated circuit chip having a digital memory is provided wherein direct access to at least a portion of the memory is prevented. Contact pads having coupling lines to couple the contact pads to the memory bus are provided. A security code can be programmed into a portion of the memory during wafer probe and test. When the integrated circuit chip is removed from the wafer the coupling lines between the contact pads and the memory bus are destroyed since the coupling lines are made to extend off of the chip.

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