Measuring method of a transistor

G - Physics – 01 – R

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356/117

G01R 31/26 (2006.01)

Patent

CA 1247258

ABSTRACT OF THE DISCLOSURE The present invention is a measuring method of a transistor for measuring a collector-to-emitter sustaining voltage in an open base configuration VCEO(sus) and when reverse bias is applied to the base of the transistor VCEX(sus). By this measuring method, a set voltage of a clamp circuit connected between the collector and the emitter of the transistor is larger than the value of the collector-to-emitter sustaining voltage VCEO(sus) or without connecting such a clamp circuit, a sustaining current larger than a current value corresponding to the minimum voltage of the collector-to-emitter sustaining voltage locus of the transistor or larger than 10% of the rated current is made to flow so that a relation between an upper limit of withstand voltage of the transistor and a breakdown resistance in a high voltage area can be clearly indicated.

515704

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