Memory access control apparatus

Details Memory access control apparatus Memory access control apparatus

G - Physics

06

F

354/237

G06F 12/02 (2006.01) G06F 3/12 (2006.01) G06F 5/10 (2006.01) G06T 1/60 (2006.01)

Patent

CA 1231463

MEMORY ACCESS CONTROL APPARATUS ABSTRACT OF THE DISCLOSURE A memory access control apparatus comprising an address detecting (CAQ) circuit for detecting a real address at which read data has been stored, a corre- spondence storing circuit (CAT) for storing a corre- spondence between a real address and a logical address, and a control circuit (IMC) for controlling a writing operation in such a way that, at a read real address detected by the address detecting circuit, a next transfer unit of data is written, after the transfer unit of data previously stored at the read real address has been read, by specifying the corresponding logical address, whereby a continuous reading can be effected without stopping due to a writing operation.

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