Memory access control system

Details Memory access control system Memory access control system

G - Physics

06

F

354/237, 352/40.

G06F 13/00 (2006.01) G06F 13/16 (2006.01)

Patent

CA 1072216

ABSTRACT OF THE DISCLOSURE A memory access control system which is provided between one or more accessing devices and a main memory composed of a plurality of independ- ently accessible logic stores and receives a request from the accessing device based on the status of the main memory to permit access to one of the logic stores. The memory access control system comprises a shift register composed of stages corresponding to the cycle time of the main memory for storing address information sufficient for identifying a busy one of the logic stores and sequentially shifting the stored content in synchronism with a clock signal and a comparator circuit for comparing the content of each stags of the shift register with address information of the logic store designated based on the request from the accessing device, receiving the request based on the result of the comparison and generating a control signal for accessing to the designated logic store. Using the shift register, one of the logic stores to be accessed can be checked whether it is busy or not, so that even if the number of logic stores is increased with an increase of the capacity of the main memory, the scale of the memory access control system is not enlarged. The shift register has stored therein also the codes of operations, the codes of the accessing devices, etc., and is capable of identification of the accessing device to which data read out from the main memory is to be send back, and a partial write control.

276836

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