G - Physics – 06 – F
Patent
G - Physics
06
F
G06F 12/02 (2006.01)
Patent
CA 2044472
MEMORY ADDRESS SPACE DETERMINATION USING PROGRAMMABLE LIMIT REGISTERS WITH SINGLE-ENDED COMPARATORS Abstract An apparatus for determining cacheable address and write-protect memory address regions in a computer system which includes a programmable single-ended limit register and a single comparator to determine each such region. A programmable limit register associated with each respective memory address region defines a boundary limit for each of the respective memory regions. A single address comparator associated with each respective limit register determines whether a memory address developed by the computer system resides between the respective boundaries provided by the value stored in the respective programmable limit register and a predefined address. The use of a single limit register and a single address comparator for each memory address region reduces the gate count and decreases the input buffer loading in the logic circuitry.
Collins Michael J.
Kelly Philip C.
Compaq Computer Corporation
Finlayson & Singlehurst
LandOfFree
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