Memory addressing device

Details Memory addressing device Memory addressing device

G - Physics

11

C

354/239

G11C 8/00 (2006.01) G11C 5/06 (2006.01) G11C 8/04 (2006.01)

Patent

CA 1218758

ABSTRACT OF THE DISCLOSURE An addressing device for a memory, such as a dynamic memory ROM or RAM, addressable by means of address words at a predetermined clock-period rate. Each address word is made up of first and second address words composed of least significant and most significant bits of the address word respectively. The first and second address words are multiplexed. The device comprises an adding circuit for incrementing the first address words in terms of a predetermined digital signal carrying words that are synchronous with the first address words and for incrementing the second address word in each address word by unity whenever said first word of said address word has bits all equal to "1", and a shift circuit looped across the adding circuit in order to deliver the first and second multiplexed address words to the memory.

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