Memory arrangement for use in a digital data processing system

Details Memory arrangement for use in a digital data processing system Memory arrangement for use in a digital data processing system

G - Physics

06

F

354/241

G06F 13/06 (1980.01)

Patent

CA 1090923

MEMORY MODULE WITH MEANS FOR CONTROLLING INTERNAL TIMING ABSTRACT A random access memory module for connection in a memory arrangement for a digital data processing system that additionally includes a high speed associative memory unit. The associative memory unit contains a multiple location address memory and a multiple location data memory wherein there is a correspondence between each address location and a data location. Each time a central processor in the system initiates a reading operation, it issues an address to define a data location. If the associative memory unit contains that address at a location in its address memory, it performs a reading memory cycle and transfers data from the corresponding location in the data memory directly to the central processor. On the other hand, if the associative memory does not contain that address, it initiates a reading memory cycle with the random access memory module. In addition, each memory module contains a margin bit decoder that decodes various binary margin signals that are transferred to it for performing various control operations. For example, these signals can alter strobe timing in the memory module. A margin signal decoder converts the incoming binary signal into an analog strobe margin signal that may have one of several magnitudes depending upon the incoming memory module.

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