Memory arrangement for use in a digital data processing system

Details Memory arrangement for use in a digital data processing system Memory arrangement for use in a digital data processing system

G - Physics

06

F

354/237

G06F 12/08 (2006.01) G06F 13/42 (2006.01)

Patent

CA 1083724

83-189 IN THE UNITED STATES PATENT AND TRADEMARK OFFICE Application of Relating to MEMORY ARRANGEMENT FOR USE IN A DIGITAL DATA PROCESSING SYSTEM Abstract of the Disclosure A memory arrangement for a digital data processing system that includes a high-speed associative memory unit and a random access backup memory unit, Each time a central processor initiates an operation to transfer the contents of a location to itself, it issues an address. If the associative memory unit which contains the data from some of the locations in the backup memory unit, contains corresponding data, it per- forms a reading memory cycle and transfers the data directly to the central processor. If the data is not available, or if the central processor is transferring data to the addressed location, the associative memory unit causes the backup memory unit to perform a corresponding memory cycle thereby to update the corresponding locations in both the associative and the back- up memory units. Other memory units and input/output units also communicate with the backup memory and the associative memory units. For example, a secondary storage device may trans- fer data to locations in the backup memory unit. If the associative memory unit contains a corresponding location, the contents in that location are modified to indicate that the data in that location has been changed.

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