Memory array

Details Memory array Memory array

G - Physics

11

C

354/223

G11C 29/00 (2006.01) G06F 11/10 (2006.01)

Patent

CA 1094224

MEMORY ARRAY Abstract of the Disclosure The present invention relates to a memory array. The array is comprised of a plurality of intersecting rows and columns with each row and column including a plurality of binary storage cells. Each cell stores one binary bit. A unit is provided for checking the parity of the bits in each row of the memory array. A unit is also provided, which is responsive to the checking unit for indicating a malfunction in the memory array. A counter is provided for counting the number of rows in which parity errors occur. Finally, a unit is provided for normally disabling the indicating unit and for enabling the indicating unit at the time the number of rows containing parity errors exceed a predetermined threshold number.

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