Memory array

H - Electricity – 01 – L

Patent

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352/82.1

H01L 27/06 (2006.01) G11C 11/40 (2006.01) G11C 11/411 (2006.01) G11C 11/414 (2006.01) H01L 27/00 (2006.01) H01L 27/02 (2006.01) H01L 27/102 (2006.01) H03F 3/04 (2006.01) H03K 3/012 (2006.01) H03K 3/289 (2006.01) H03K 19/091 (2006.01)

Patent

CA 1041664

ABSTRACT: Memory array built up from memory cells which each comprise two cross-coupled transistors of the one conductivity type the collector circuits of which include load transistors of the other conductivity type, at least one of the bases of the cross-coupled transistors being connected via the main current path of a transis- tor to an associated bit line, whilst the base of the latter transistor, the bases of the load transistors and the emitters of the cross-coupled transistors are interconnected so as to form a node, each of the memory cells being connected to an associated row selection line and to an associated column selection circuit, characterized in that the emitters of the load transis- tors in each cell are connected to the associated row se- lection line whilst the bit line of each memory cell is connected to the column selection circuit, the nodes of all the memory cells being directly interconnected.

203957

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