Memory block address determination circuit

Details Memory block address determination circuit Memory block address determination circuit

G - Physics

06

F

354/237

G06F 12/06 (2006.01)

Patent

CA 2005699

MEMORY BLOCK ADDRESS DETERMINATION CIRCUIT Abstract of the Disclosure An adder and a comparator form portions of a modular memory address block determination circuit. The starting address of the first block and the enable signal of the first block are added to produce the starting address of the second block. This procedure is repeated for each block. The determined starting address for each block is compared with the requested memory address and, unless the block is inhibited or disabled, if equal a signal indicates the match. The circuit is used on a circuit board which emulates three conventionally separate memory circuit boards. The registers for each emulated board are provided and appropriate bus signals are developed.

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