Memory cell

Details Memory cell Memory cell

G - Physics

11

C

352/82.3

G11C 7/00 (2006.01) G11C 11/412 (2006.01) G11C 11/417 (2006.01) G11C 11/42 (2006.01) H03K 3/356 (2006.01)

Patent

CA 1065056

Abstract A semiconductor memory cell whose supply voltage is decoupled from the cell voltage bus during a write operation. Automatic return of the bus to the supply voltage level once the static state is reached, even though a write command is still present, is achieved by supplying operating voltage to the cell bus from one of the data lines via a conducting transistor.

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