Memory cells enhanced for resistance to single event upset

Details Memory cells enhanced for resistance to single event upset Memory cells enhanced for resistance to single event upset

G - Physics

11

C

G11C 11/34 (2006.01) G11C 11/412 (2006.01) G11C 29/52 (2006.01)

Patent

CA 2482631

Method and apparatus are described for providing memory cells enhanced for resistance to single event upsets. In one embodiment, transistors are coupled between cross coupled inverters of a latch, thus in a small area providing both single-event-upset resistivity most of the time, and high speed during writing to the memory cell. Alternatively, inductors coupled between inverters of a latch may be used.

La présente invention a trait à un procédé et un appareil permettant la réalisation de cellules de mémoires améliorées pour une résistance à des perturbations isolées. Dans un mode de réalisation, des transistors sont reliés entre des inverseurs interconnectés d'un verrou, fournissant ainsi dans une petite surface à la fois une résistivité à la perturbation isolée la plupart du temps, et une vitesse élevée lors de l'inscription dans la cellule de mémoire. En variante, on peut utiliser des bobines d'inductance reliées entre des inverseurs d'un verrou.

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