Memory control device for an assay apparatus

Details Memory control device for an assay apparatus Memory control device for an assay apparatus

G - Physics

06

K

G06K 9/20 (2006.01) G05B 19/414 (2006.01) G06F 9/445 (2006.01) G06F 12/06 (2006.01)

Patent

CA 2166804

A memory control arrangement includes a processor (10) for performing program data and configuration operations, a memory (13, 14) for storing program and configuration data in different parts of the memory, and a memory control device (15) for allowing the processor to access the different parts of the memory during different operating conditions of the processor.

Le dispositif de commande à mémoire est constitué d'un processeur (10) exécutant les logiciels et effectuant les opérations de gestion des données et de configuration, d'une mémoire (13, 14) pour stocker les logiciels et les données de configuration en différents endroits de la mémoire, et d'un organe (15) de gestion de la mémoire grâce auquel le processeur peut avoir accès aux différents emplacements mémoire pendant les différents états de fonctionnement du processeur.

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