Memory control system

Details Memory control system Memory control system

G - Physics

06

F

354/237

G06F 12/06 (2006.01)

Patent

CA 1305562

ABSTRACT OF THE DISCLOSURE A system for controlling the addressing of a memory on a predetermined multi-megabyte decode boundary, An address shifter is coupled between CPU address lines and backplane area bussed address lines. The address shifter is controlled in accordance with the control signal determined by the memory array of a largest capacity of all memory arrays. The control signal has different states to control the address shifter to couple different address bit patterns therethrough to the backplane area address bus as a function of the selected control signal state.

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