Memory controller and data processing system

Details Memory controller and data processing system Memory controller and data processing system

G - Physics

06

F

G06F 12/10 (2006.01) G06F 12/06 (2006.01) G06F 13/16 (2006.01)

Patent

CA 2079353

JA9-91-027 MEMORY CONTROLLER AND DATA PROCESSING SYSTEM ABSTRACT In the case where memory units are allocated to a plurality of interleavable banks, to provide a function for forming a plurality of memory maps which is comprised of the memory units in all banks arranged in predetermined different orders according to the number of said banks, detecting that an address area within a predetermined range involving a CPU address or addresses belongs to which of the memory units on each of a plurality of said memory maps, and determining whether each of detected memory units belongs to interleavable banks each other.

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