Memory controller for direct or interleave memory accessing

Details Memory controller for direct or interleave memory accessing Memory controller for direct or interleave memory accessing

G - Physics

06

F

G06F 12/06 (2006.01) G11C 8/12 (2006.01)

Patent

CA 2050950

A data processing system includes a processor for accessing a memory in either a direct mode or an indirect mode. The memory includes at least two memory banks and two decoders for decoding bank addresses. The decoders produce bank select signals. In direct mode, the decoder outputs are generated according to which bank is addressed. In interleave mode, the two decoder outputs are ANDed to select both banks covering the address range of the selected banks.

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