Memory controller with adaptive processor interface port

Details Memory controller with adaptive processor interface port Memory controller with adaptive processor interface port

G - Physics

06

F

G06F 13/14 (2006.01)

Patent

CA 2491923

A computer system architecture and memory controller (502) for close-coupling within a hybrid computing system using an adaptive processor interface port ("APIP") (524) added to, or in conjunction with, the memory and I/O controller chip of the core logic. Memory accesses to and from this port, as well as the main microprocessor bus, are then arbitrated by the memory control circuitry (514) forming a portion of the controller chip. In this fashion, both the microprocessors and the adaptive processors of the hybrid computing system exhibit equal memory bandwidth and latency. In addition, because it is a separate electrical port from the microprocessor bus, the APIP is not required to comply with, and participate in, all FSB protocol (512). This results in reduced protocol overhead which results higher yielded payload on the interface.

L'invention porte sur l'architecture et le contrôleur de mémoire d'un ordinateur permettant un couplage étroit dans un système informatique hybride, et utilisant un port d'interface de processeur adaptatif (APIP) s'ajoutant à ou associé à, la mémoire et à la puce du contrôleur d'E/S de la logique centrale. Les accès à la mémoire vers et à partir de ce port et vers et à partir du bus principal du microprocesseur sont alors arbitrés par le circuit de commande formé par une partie de la puce du contrôleur. Ainsi, les microprocesseurs et les processeurs adaptatifs du système informatique hybride présentent-ils à la fois une largeur de bande de mémoire et une latence, égales. Il en résulte une réduction du temps système et par-là une plus forte charge utile efficace sur l'interface.

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