Memory device

Details Memory device Memory device

G - Physics

11

C

352/40, 345/6

G11C 11/42 (2006.01) G02F 1/1362 (2006.01) G06F 11/20 (2006.01) G11C 29/00 (2006.01) H01L 27/108 (2006.01)

Patent

CA 1175938

- 48 - Abstract of the Disclosure Disclosed is a memory device having a plurality of memory cells arranged in a matrix form; address buses connected to the memory cells and forming respective rows of the matrix; and data buses connected to the memory cells and forming respective columns of the matrix. The address buses or the data buses are formed by paired bus lines, and bridge lines are formed between one and the other of the paired bus lines.

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