Memory device and method implementing wordline redundancy...

Details Memory device and method implementing wordline redundancy... Memory device and method implementing wordline redundancy...

G - Physics

06

F

352/82.24

G06F 11/20 (2006.01) G11C 29/00 (2006.01)

Patent

CA 1314988

ABSTRACT OF THE DISCLOSURE The invention provides a semiconductor memory device and method for implementing wordline redundancy with no access penalty in such a device. A redundant word decoder compares an incoming address signal with a list of defective addresses and, in response to the comparison, produces at least one comparison signal to control the propagation of a redundant driver signal along at least one redundant wordline. A main trigger receives the comparison signal and, in response thereto, triggers the firing of a main wordline driver to produce a main driver signal. The main wordline driver and the redundant word decoder are responsive to opposite states of the comparison signal, such that, for a given comparison signal, only one of the main driver signal and redundant driver signal is applied to a memory array.

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