Memory device for resistance-based memory applications

G - Physics – 11 – C

Patent

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Details

G11C 7/06 (2006.01) G11C 7/10 (2006.01) G11C 7/12 (2006.01) G11C 7/14 (2006.01) G11C 11/16 (2006.01)

Patent

CA 2735725

In a particular embodiment, a memory device (100) is disclosed that includes a memory cell (226) including a resistance based memory element (228) coupled to an access transistor (230). The access transistor has a first oxide thickness to enable operation of the memory cell at an operating voltage. The memory device also includes a first amplifier (202) configured to couple the memory cell to a supply voltage (Vamp) that is greater than a voltage limit to generate a data signal based on a current through the memory cell. The first amplifier includes a clamp transistor (216) that has a second oxide thickness that is greater than the first oxide thickness. The clamp transistor is configured to prevent the operating voltage at the memory cell from exceeding the voltage limit.

La présente invention porte, dans un mode de réalisation particulier, sur un dispositif de mémoire (100) qui comprend une cellule de mémoire (226) comprenant un élément de mémoire à résistance (228) couplé à un transistor d'accès (230). Le transistor d'accès a une première épaisseur d'oxyde pour permettre le fonctionnement de la cellule de mémoire à une tension de fonctionnement. Le dispositif de mémoire comprend également un premier amplificateur (202) configuré pour coupler la cellule de mémoire à une tension d'alimentation (Vamp) qui est plus importante qu'une limite de tension pour générer un signal de données sur la base d'un courant à travers la cellule de mémoire. Le premier amplificateur comprend un transistor de fixation de niveau (216) qui a une seconde épaisseur d'oxyde qui est plus importante que la première épaisseur d'oxyde. Le transistor de fixation de niveau est configuré pour empêcher que la tension de fonctionnement au niveau de la cellule de mémoire ne dépasse la limite de tension.

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