Memory device with charge storage barrier structure

Details Memory device with charge storage barrier structure Memory device with charge storage barrier structure

H - Electricity

01

L

H01L 27/10 (2006.01) G11C 11/34 (2006.01) H01L 21/8232 (2006.01) H01L 21/8239 (2006.01) H01L 27/105 (2006.01) H01L 29/772 (2006.01)

Patent

CA 2220782

A memory device includes a memory node (1) to which charge is written through a tunnel barrier configuration (2) from a control electrode (9). The stored charge effects the conductivity of a source/drain path (4) and data is read by monitoring the conductivity of the path. The charge barrier configuration comprises a multiple tunnel barrier configuration, which may comprise alternating layers (16) of polysilicon of 3nm thickness and layers (15) of Si3N4 of 1 nm thickness, overlying polycrystalline layer of silicon (1) which forms the memory node. Alternative barrier configurations (2) are described, including a Schottky barrier configuration, and conductive nanometer scale conductive islands (30, 36, 44), which act as the memory node, distributed in electrically insulating matrix.

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