Memory diagnostic apparatus and method

Details Memory diagnostic apparatus and method Memory diagnostic apparatus and method

G - Physics

06

F

354/126, 354/224

G06F 11/00 (2006.01) G06F 12/00 (2006.01) G06F 12/06 (2006.01) G11C 29/00 (2006.01) G11C 29/32 (2006.01)

Patent

CA 1315409

70840-145 MEMORY DIAGNOSTIC APPARATUS AND METHOD ABSTRACT OF THE DISCLOSURE A system console is enabled to read registers from memory boards and to set registers within the memory boards which control the disabling of one or more memory arrays. The informa- tion read from the memory boards is indicative at least of which of the memory arrays has malfunctioned. The registers are within a memory logic array, one of which is disposed upon each of the memory boards and also upon a memory controlling unit, the memory logic arrays being coupled together by a bit serial scan bus. In a preferred embodiment of the invention the memory logic arrays are comprised of a highly integrated gate array semiconductor device, each of which is identical. Each memory logic array is provided with a base address input from a preceding memory logic array and computes a base address for a subsequent memory logic array. A memory logic array which has a portion of an associated memory disabled automatically determines a revised base address for the subsequent memory logic array, thereby initiating the automatic reallocation of memory board base addresses of all sub- sequent memory boards.

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