Memory diagnostic arrangement

Details Memory diagnostic arrangement Memory diagnostic arrangement

G - Physics

11

C

354/224

G11C 29/00 (2006.01) G06F 11/10 (2006.01) G06F 11/16 (2006.01) G11C 29/02 (2006.01)

Patent

CA 1058324

MEMORY DIAGNOSTIC ARRANGEMENT Abstract of the Disclosure A diagnostic system is disclosed for detecting malfunctions in the access circuitry utilized to control the reading, writing, and refreshing of a plurality of semiconductor memory modules. More specifically, a pair of access circuits are provided for each module with each access circuit only controlling the accessing of predetermined bits of each word stored in that module. During read or write operations, the output signals generated by each of the two access circuits for application to the memory elements in that module are "compared" to ensure that the memory elements are being properly accessed. During refresh operations, the outputs of each pair of access circuits are also "matched" to ensure the integrity of the refresh operation.

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