G - Physics – 06 – F
Patent
G - Physics
06
F
354/224
G06F 11/00 (2006.01) G06F 11/10 (2006.01) H03M 13/13 (2006.01)
Patent
CA 1128664
30.11.78 1 PHN.9078 ABSTRACT "Memory, incorporating error detection and correction" A word location for a user word in a memory not only contains the bit locations for the actual data but also each time one parity bit for the parity over the entire word location, and per word location there is also one correction bit. Each time a fixed number of word locations are grouped to form a memory location for the storage of a memory word. When a word location is read by a data user, the parity bit indicates whether the word location contains none or one bit error. The occurrence of two bit errors in a single word location cannot be detected in this manner. If the user word does not contain errors, it becomes available to the data user, the correc- tion bit thereof not providing further information in these circumstances. If the user word contains an error, the other word locations of the same memory location and also the associated correction bits are read. The set of parity bits and correction bits can then correct one arbitrary bit error in the memory word. In given cases, a plurality of bit errors can be corrected. notably if they are each time situated in bit positions of the same rank within the word locations for the user words. The chance that a multiple error has exactly this configuration can be enhanced by a suitable arrangement of the bit locations in a memory Thus, a limited amount of redundancy suffices 30.11.78 2 PHN.9078 in many cases. Memory words in different memory banks may have the correction bits in common.
326467
N.v. Philips Gloeilampenfabrieken
Van Steinburg C.e.
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