Memory interleave system

Details Memory interleave system Memory interleave system

G - Physics

06

F

G06F 12/00 (2006.01) G06F 12/06 (2006.01)

Patent

CA 2480841

A memory interleave system includes M (M is 2p o where p is a natural number) memory banks, N (a natural number) CPUs, N address generating units, and M memory control units. Each memory bank includes a plurality of memories. The CPUs output memory requests as access requests to the memory banks. Each memory request contains the first bank address which is the address of the memory bank and the first intra-bank address which is the address of a memory in the memory bank. The address generating units respectively correspond to the CPUs. Each address generating unit receives a memory request from a corresponding CPU, and newly generates and outputs the second intra-bank address and the second bank address by using the first intra-bank address and the first bank address which are contained in the memory request. The memory control units respectively correspond to the memory banks. Each memory control unit performs memory bank access control on the basis of the second intra-bank address output from the address generating unit. A memory control unit which performs access control is selected on the basis of the second bank address output from the address generating unit.

Affiliated with

Also associated with

Rating

Memory interleave system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory interleave system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory interleave system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-2012162