Memory manager for hierarchical graphic structures

Details Memory manager for hierarchical graphic structures Memory manager for hierarchical graphic structures

G - Physics

06

F

354/241

G06F 12/08 (2006.01) G06T 17/00 (2006.01)

Patent

CA 2028322

Video random access memory having a random array and serial buffer is employed to speed the replication of structure state information used in the processing of hierarchical graphic data structures. Specialized circuitry in the video RAM and associated VRAM sequencer are used to perform a rapid transfer of structure state information from one row of the VRAM (the parent row) to a second VRAM row (the child row). The VRAM sequencer is modified to perform back to back read data transfer and write data transfer operation in response to a single graphics processor command. The return to previous structure state can be accomplished by readdressing the VRAM row containing the previous structure state.

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