Memory means with multiple word read and single word write

Details Memory means with multiple word read and single word write Memory means with multiple word read and single word write

G - Physics

06

F

354/238

G06F 12/04 (2006.01)

Patent

CA 1256217

70840-64 ABSTRACT OF THE DISCLOSURE A memory wherein the basic unit of information is a multiple of word size providing, in the read aspect, for reads of multiple information units in a single read operation and, in the write aspect, for writes of a single word. In the read aspect, the memory includes a memory unit having a memory store for storing units of information and a memory unit controller. Each read request includes an initial address and specifies a number of units of information. The memory unit controller is responsive to a request specifying one or more units of information for generating in a single memory operation a sequence of addresses, the sequence of addresses beginning at the initial address and containing a number of addresses equal to the specified number of information units. The memory store includes a first memory plane containing storage locations having successive even addresses and a second memory plane containing storage locations having successive odd addresses. The first and second memory planes are responsive to each address provided thereto to read an information unit from the corresponding location in one of the memory planes and to concurrently read the information unit from the corresponding next location in the other memory plane. The memory unit controller provides the initial and each alternate successive address of a sequence of addresses to the first and second memory planes to read corresponding pairs of information units therefrom and provides each successive address of a sequence of addresses to the memory output selector to select and read the successive memory information units of a sequence.

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